The present invention relates to a semiconductor integrated circuit device and, more particularly, to a dynamic semiconductor memory device using a trench capacitor as a capacitor element constituting a memory cell.
The memory cell of a dynamic semiconductor memory device (to be referred to as a DRAM hereinafter) is made up of a capacitor and a transfer insulated gate transistor. To increase the integration degree of the DRAM, capacitors with larger capacitance values are desirably formed in a smaller area. One means for realizing such a structure is a trench capacitor obtained by constituting a capacitor using a trench formed in a silicon substrate.
Of trench capacitors, a BEST (BuriEd STrap) cell receives a great deal of attention as a capacitor which can cope with a mass DRAM in the Gbit (Gigabit) class.
Such a BEST cell is described in the following references:
"International Electron Devices Meeting", 1993, pp. 627-630, and
"A 0.6 .mu.m.sup.2 256 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST)", L. Nesbit et al., Dec. 5-8, 1993.
The trench capacitor of the BEST cell is obtained by forming an n-buried well in a p-silicon substrate, forming a trench to reach the n-well, and forming a storage electrode in this trench. The n-buried well functions as a plate electrode.
The BEST cells can be micropatterned and are effective to increase the integration degree of memory cell arrays. However, since the plate electrode is formed by the n-buried well, a chip including circuits such as sense amplifiers formed around memory cell arrays is difficult to downsize.
The n-buried well is formed by heavily doping an n-impurity in a deep portion in the substrate, and thermally diffusing the doped n-impurity over a wide range in the substrate. The n-impurity diffuses in not only a direction perpendicular to the substrate but also a direction horizontal to the substrate. For this reason, the area of the n-buried well is large.
Forming the n-buried well requires a long-time thermal diffusion step, which poses problems such as high manufacturing cost in terms of mass production.
In consideration of these situations, a recent BEST cell is improved such that an n-impurity in solid phase is diffused from a trench into a substrate to form an n-diffusion layer around the trench, and this n-diffusion layer is used as a plate electrode.
FIG. 24 is a sectional view showing the element structure of one BEST cell of this type.
As shown in FIG. 24, a trench 142 is formed in a semiconductor substrate 141 made of p-silicon. An n.sup.+ -diffusion region 143 heavily containing an n-impurity is formed in a portion of the semiconductor substrate 141 facing trench 142. The n.sup.+ -diffusion region 143 serves as the plate electrode of the trench capacitor. A capacitor insulating film 144 made of, e.g., a silicon oxide film is formed on a surface inside the trench 142. A storage electrode 145 of the trench capacitor is formed to bury the trench 142 except for an upper portion of the trench 142. An n.sup.+ -conductive layer 146 is buried in the upper portion of the trench.
A transfer transistor 147 and a thick field oxide film 148 are formed around the trench capacitor on the substrate 141. The transfer transistor 147 is formed by sequentially stacking a gate oxide film 149 and a gate electrode 150 on the substrate 141, and forming source and drain regions 151 and 152 each made of an n-diffusion region in the substrate surface region. The source region 151 is electrically connected to the n.sup.+ -conductive layer 146 through part of the side wall of the trench 142.
The trench capacitor has the electrode 145 formed inside the trench through the capacitor insulating film 144 formed on the surface inside the trench 142, and the heavily doped n.sup.+ -diffusion region 143 which is formed in the portion of the semiconductor substrate 141 facing the trench 142 and used as a counter electrode. A voltage 1/2 the voltage used inside the DRAM is applied across the counter electrode and the electrode formed inside the trench. In general, the capacitor insulating film 144 has a thickness as small as 10 nm or less, and the n.sup.+ -diffusion region 143 has an impurity concentration as sufficiently high as 5.times.10.sup.18 /cm.sup.3.
As the integration degree of the DRAM increases, the frontage of the trench becomes smaller. The capacitance value of the capacitor must be kept large by making the trench deeper. The n.sup.+ -diffusion region 143 is formed by doping the n-impurity, forming the insulating film serving as a solid phase diffusion source in the trench, and diffusing the n-impurity in solid phase from the insulating film into the semiconductor substrate 141 through the side surface inside the trench. After that, the insulating film serving as the diffusion source is removed from the trench. In this case, if the trench is deep with a small frontage, i.e., the aspect ratio of the trench is high, the insulating film serving as the diffusion source is difficult to completely remove from the trench.
If the insulating film serving as the diffusion source is left on the bottom of the trench, i.e., the end portion of the trench, the trench becomes shallow. Accordingly, the trench capacitor cannot ensure a sufficient capacitance value, and data storage characteristics degrade.
Note that the aspect ratio of a current trench is almost 20 (depth of about 7 .mu.m/frontage of about 0.3 .mu.m). FIGS. 25A and 25B respectively show sections of a BEST cell having a trench with an aspect ratio of almost 20.
As shown in FIG. 25A, a frontage F of the opening portion of the trench 142 is about 0.3 .mu.m, and a depth D thereof is about 7 .mu.m. An aspect ratio D/F is as high as about 20. The trench 142 having such a high aspect ratio is tapered by current manufacturing techniques. The insulating film serving as the diffusion source is generally removed by dry etching. The frontage F of the opening portion of the trench 142 is large. For this reason, fresh unreacted etchant gas is sufficiently supplied from outside the trench 142, and the insulating film can be easily removed.
To the contrary, the width of the distal end portion of the trench 142 is small, and the etchant gas reaches the end portion of the trench while reacting with the insulating film inside the trench 142. For this reason, the amount of fresh unreacted etchant gas becomes smaller at the end portion than at the opening portion, and the etching effect for the insulating film becomes very poor.
From these situations, the insulating film is very difficult to completely remove from the trench 142.
Accordingly, an insulating film 160 serving as the solid phase source is left on the bottom of the trench 142, as shown in FIG. 25B. The insulating film 160 left on the bottom of the trench 142 decreases an effective depth D' of the trench 142 functioning as a trench capacitor T.C. to decrease the capacitance of the trench capacitor T.C. Although the insulating film 160 can be completely removed by etching the insulating film 160 for a long time, this leads to a long manufacturing time and high manufacturing cost.
The micropatterning of memory cells of the DRAM will advance to realize a memory capacitance in the Gbit class or higher. In the trench capacitor, a trench having an aspect ratio of 20 or higher will be formed. From these viewpoints, the insulating film 160 may become more difficult to remove.